Formal Verification of Distributed Master-Slave Finite State Machine(Conference Paper)
- aRT-RK Institute For Computer Based Systems, Novi Sad, Serbia
- bUniversity of Novi Sad, Faculty of Technical Sciences, Novi Sad, Serbia
Abstract
Recently, the distributed master-slave finite state machine appeared as a solution to govern a pair of transaction coordinators operating in the master-slave mode. In this paper, we formally verify the correctness of that solution using process algebra CSP and the model checker PAT. The CSP model consists of CSP processes modelling the transaction coordinators and individual master-slave finite state machines. During verification, altogether 30 assertions were automatically checked by PAT and found to be valid. © 2021 IEEE.
Indexed keywords
| Engineering controlled terms: | Distributed computer systemsFault toleranceModel checkingParallel programming |
|---|---|
| Engineering uncontrolled terms | CSP modelFinite states machineMaster slaveModel checkerProcess algebrasProcess-modelsTransactional memory |
| Engineering main heading: | Formal verification |
Funding details
| Funding sponsor | Funding number | Acronym |
|---|---|---|
| Ministarstvo Prosvete, Nauke i Tehnološkog Razvoja | 451-03-68/2020-14/200156 | MPNTR |
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ACKNOWLEDGMENT This research has been partly supported by the Ministry of Education, Science and Technological Development through the project no. 451-03-68/2020-14/200156: “Innovative scientific and artistic research from the FTS (activity) domain”.
- ISBN: 978-166542584-1
- Source Type: Conference Proceeding
- Original language: English
- DOI: 10.1109/TELFOR52709.2021.9653241
- Document Type: Conference Paper
- Publisher: Institute of Electrical and Electronics Engineers Inc.
© Copyright 2022 Elsevier B.V., All rights reserved.
Cited by 1 document
(2022) 2022 30th Telecommunications Forum, TELFOR 2022 - Proceedings